1) Field
This invention relates to an optical integrated device (semiconductor optical integrated device) which includes a high-performance optical multiplexer/demultiplexer semi-insulating buried hetero-structure type semiconductor optical coupler) used, for example, for a bulk optical communication system.
2) Description of the Related Art
At present, research and development for implementing a small-sized high-functional semiconductor optical integrated device by integrating optical active devices (active parts) such as a semiconductor laser, a semiconductor optical amplifier (SOA), an optical modulator and an optical detector and optical passive devices (passive parts) such as an optical waveguide and an optical multiplexer/demultiplexer (optical coupler) on a single semiconductor substrate is being carried out energetically.
In many semiconductor optical integrated devices, a structure is used wherein a plurality of active parts such as semiconductor lasers and SOAs are disposed on a single semiconductor substrate and are coupled by optical waveguides and/or optical multiplexers/demultiplexers (optical couplers).
An example of the structure just described is a semiconductor optical integrated device disclosed in Japanese Patent Laid-Open No. 2005-223300. The semiconductor optical integrated device is formed as an SOA optical gate switch 104, for example, as shown in FIG. 7(A). Referring to FIG. 7(A), the SOA optical gate switch 104 has eight input ports ch1 to ch8 and a single output port ch9 and includes an SOA array (8-ch SOA array) 100 including eight SOAs 100A, a single SOA (1-ch SOA) 101 and a single 8-input 1-output FFC type optical coupler (8×1-ch FFC type optical coupler; hereinafter referred to simply as optical coupler) 102. The components mentioned are connected by optical waveguides 103 to form the SOA optical gate switch 104.
For example, as shown in FIG. 7(A), the SOA optical gate switch 104 has an 8×1-ch optical gate switch function for selecting one signal light from among eight signal lights (input signal lights) individually inputted to the SOAs 100A which form the 8-ch SOA array 100 through the eight input ports ch1 to ch8, amplifying the selected signal light by means of the 1-ch SOA 101 and outputting the amplified signal light as output signal light from the output port ch9.
In particular, the SOA optical gate switch 104 injects current at the same time into one of the eight SOAs (one SOA provided on one of the eight input ports ch1 to ch8) which is a component of the 8-ch SOA array 100 and into the 1-ch SOA 101 thereby to provide optical gain to the signal light propagating along the optical path of the selected SOA, but does not inject current into the remaining seven ones of the SOAs (remaining seven SOAs individually provided on the remaining seven ones of the eight input ports ch1 to ch8) of the 8-ch SOA array 100. Then, by utilizing a high absorption coefficient of the SOAs, signal lights propagating along the optical paths of the remaining seven ones of the SOAs are quenched to implement the optical gate switch function.
Further, for example, as seen in FIG. 7(A), in the SOA optical gate switch 104, signal lights from optical fibers (not shown) are inputted individually to the input ports ch1 to ch8 on the 8ch SOA array 100 side provided on one of device end faces, for example, using a lens or a PLC device (planar light circuit device), and signal light is outputted from the output port ch9 on the 1-ch SOA 101 side provided on the other one of the device end faces to an optical fiber (not shown), for example, using a lens or a PLC device (plane light circuit device).
Incidentally, such an SOA optical gate switch 104 as described above is produced on a single semiconductor substrate (here, InP substrate) 105 wherein the entire device has the [100] plane direction, for example, as seen in FIGS. 7(B) to 7(D), and an optical waveguide structure which forms the SOAs 100A and 101, optical coupler 102 and optical waveguides 103 has a channel waveguide structure wherein an optical active layer (here, InGaAs active layer) 107 and an optical waveguide layer (here, InGaAsP waveguide layer) 110 which individually have a high refractive index are provided as a rectangular core layer in order to secure a high signal light guide efficiency and a single mode property.
In particular, for example, as seen in FIG. 7(B), the optical waveguide structure of the 1-ch SOA 101 has a structure formed by stacking a lower cladding layer (here, n-InP cladding layer) 106, an InGaAs active layer 107 and an upper cladding layer (here, p-InP cladding layer) 108 in order. It is to be noted that also the SOAs 100A which form the 8-ch SOA array 100 individually have an optical waveguide structure similar to that of the 1-ch SOA 101. Further, for example, as seen in FIGS. 7(C) and 7(D), the optical coupler 102 and the optical waveguide 103 individually have an optical waveguide structure wherein the lower cladding layer (here, n-InP cladding layer) 106, InGaAsP waveguide layer 110 and upper cladding layer (here, p-InP cladding layer) 108 are stacked in order.
Further, for example, as seen in FIGS. 7(A) to 7(D), the SOAs 100A and 101 individually have a semi-insulating buried-heterostructure capable of implementing both of a good current injection efficiency and reduction of the dielectric capacitance of the device, and the opposite sides of the channel waveguide structures 100A, 101, 102 and 103 are buried in a burying layer (here, semi-insulating InP burying layer) 109 formed from a semi-insulating semiconductor material (high-resistance semiconductor material).
While the burying layer 109 can be formed by depositing a semi-insulating semiconductor material on the opposite sides of the channel waveguide structures 100A, 101, 102, and 103, for example, using a metal organic chemical vapor deposition method (hereinafter referred to as MOCVD method), where the directions of the channel waveguide structures to be buried have various angles with respect to the crystal face of the substrate as seen in FIG. 7(A), the growth of the burying layer 109 formed from a semi-insulating semiconductor material must be performed using such a method (method wherein an organic chlorine material is added) as disclosed, for example, in Japanese Patent Laid-Open No. 2005-223300.
Here, if the growth of the semi-insulating semiconductor burying layer 109 is carried out using the method disclosed in Japanese Patent Laid-Open No. 2005-223300, then, for example, as seen in FIGS. 7(B) to 7(D), the semi-insulating semiconductor burying layer 109 having a flat face over a width of approximately 10 to 20 μm toward the opposite sides from the center of the waveguide at an upper portion thereof is formed. Then, an inclined face (for example, an inclined face having a determined semiconductor crystal plane direction such as a [311] B face) having a predetermined angle with respect to the substrate 105 is formed at a terminal end (in particular, a side portion of the burying layer 109) of the flat face such that the burying layer 109 does not exist on the outer side of the inclined face.
It is to be noted that Japanese Patent Laid-Open No. Hei 8-181389 discloses a technique wherein, where the opposite sides of a waveguide are buried by a semi-insulating semiconductor material, a dummy portion is formed and the semi-insulating semiconductor material is filled into a groove between the waveguide and the dummy portion such that a portion of a side face of the groove at which the crystal growth speed is high is formed with an increased width, whereby a semiconductor burying structure wherein the opposite sides of the waveguide are buried flat can be implemented even if the semiconductor burying structure is configured from waveguides having directions different from each other. In particular, Japanese Patent Laid-Open No. Hei 8-181389 discloses that the width of a groove to be formed around an optical waveguide is adjusted in response to the direction of the waveguide to cancel the difference in the growth speed arising from a difference in the crystal face azimuth on a mesa side face to form a generally flat burying layer.